Capacitor, method of controlling the same, and transistor including the same

ABSTRACT

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: 
     
       
         
           
             
               V 
               MAX 
             
             = 
             
               
                 ( 
                 
                   1 
                   + 
                   
                     
                       
                         ❘ 
                         &#34;\[LeftBracketingBar]&#34; 
                       
                       
                         Z 
                         2 
                       
                       
                         ❘ 
                         &#34;\[RightBracketingBar]&#34; 
                       
                     
                     
                       
                         ❘ 
                         &#34;\[LeftBracketingBar]&#34; 
                       
                       
                         Z 
                         1 
                       
                       
                         ❘ 
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                 ) 
               
               ⁢ 
               
                 t 
                 F 
               
               ⁢ 
               
                 E 
                 FM 
               
             
           
         
       
     
     where V MAX  is a capacitance boosting operating voltage, Z 1  is impedance of the ferroelectric film, Z 2  is impedance of the dielectric film, t F  is a thickness of the ferroelectric film, and E FM  is an electric field applied to the ferroelectric film having a maximum polarization.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.17/116,097, filed on Dec. 9, 2020, which claims the benefit of KoreanPatent Application No. 10-2020-0057191, filed on May 13, 2020, in theKorean Intellectual Property Office, the entire contents of each ofwhich are incorporated herein in its entirety by reference.

BACKGROUND 1. Field

The present disclosure relates to a capacitor, a method of controllingthe same, and a transistor including the same.

2. Description of Related Art

With the development of technology, devices such as transistors andcapacitors continue to be scaled down in size. Scaled-down devices havea limited thickness. Accordingly, there is an increasing demand formaterials having a high dielectric constant and structures thereof.

With regard to the materials having a high dielectric constant andstructures thereof, research is being conducted on the effect ofboosting capacitance using negative capacitance. The capacitanceboosting effect may sharply increase the dielectric constant of acapacitor when a voltage is applied to the capacitor.

SUMMARY

An aspect of the present disclosure provides an electronic device havinga capacitance boosting effect.

An aspect of the present disclosure provides a capacitor having acapacitance boosting effect.

An aspect of the present disclosure provides a capacitor having atransistor boosting effect.

Another aspect of the present disclosure also provides a method ofcontrolling a capacitor having a capacitance boosting effect.

However, aspects of the present disclosure are not limited to the abovedisclosure.

Additional aspects will be set forth in part in the description whichfollows and, in part, will be apparent from the description, or may belearned by practice of the presented embodiments of the disclosure.

In an aspect, provided is a method of controlling a capacitor comprisinga first electrode, a second electrode provided on the first electrode, aferroelectric film provided between the first electrode and the secondelectrode, and a dielectric film provided between the ferroelectric filmand the second electrode, the method comprising controlling an impedanceof the ferroelectric film and an impedance of the dielectric film suchthat a control voltage applied between the first electrode and thesecond electrode is equal to a capacitance boosting operating voltage,wherein the capacitance boosting operating voltage is determined byEquation 1:

$\begin{matrix}{V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}} & \left\lbrack {{Equation}1} \right\rbrack\end{matrix}$

where V_(MAX) is a capacitance boosting operating voltage, Z₁ is theimpedance of the ferroelectric film, Z₂ is the impedance of thedielectric film, t_(F) is a thickness of the ferroelectric film, andE_(FM) is an electric field applied to the ferroelectric film having themaximum polarization change produced thereto.

The ferroelectric film may include a conductance component and acapacitance component connected in parallel, and the dielectric film mayinclude a conductance component and a capacitance component connected inparallel.

An angular frequency of the control voltage may be determined such thatthe control voltage is equal to the capacitance boosting operatingvoltage. The capacitance boosting operating voltage may be determined bythe Equation 2:

$\begin{matrix}{V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}}} & \left\lbrack {{Equation}2} \right\rbrack\end{matrix}$

where G₁ is conductance of the ferroelectric film, C₁ is capacitance ofthe ferroelectric film, G₂ is conductance of the dielectric film, C₂ iscapacitance of the dielectric film, ω is the angular frequency of thecontrol voltage, Ps is polarization of the ferroelectric film when theelectric field E_(FM) is applied to the ferroelectric film, α is astability parameter, and β is a skewness parameter.

A magnitude ratio (|Z₂|/|Z₁|) of the impedance of the dielectric film tothe impedance of the ferroelectric film may be 0.01 or greater.

The current density of current flowing through the dielectric film andthe ferroelectric film may be 1 mA/cm² or less.

Spontaneous polarization of the ferroelectric film may be 20 μC/cm² orgreater.

A dielectric dissipation factor of the dielectric film may be 0.1 orless.

In an aspect, provided is capacitor comprising a first electrode, asecond electrode provided on the first electrode, a ferroelectric filmprovided between the first electrode and the second electrode, and adielectric film provided between the ferroelectric film and the secondelectrode, the method comprising the step of controlling impedance ofthe ferroelectric film and impedance of the dielectric film to make acontrol voltage applied between the first electrode and the secondelectrode equal to a capacitance boosting operating voltage, and thecapacitance boosting operating voltage is determined by the followingequation:

$V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}$

where V_(MAX) is a capacitance boosting operating voltage, Z₁ isimpedance of the ferroelectric film, Z₂ is impedance of the dielectricfilm, t_(F) is a thickness of the ferroelectric film, and E_(FM) is anelectric field applied to the ferroelectric film having the maximumpolarization change produced thereto.

The ferroelectric film may include a conductance component and acapacitance component connected in parallel, and the dielectric film mayinclude a conductance component and a capacitance component connected inparallel.

The method may further include controlling an angular frequency of thecontrol voltage such that the control voltage is equal to thecapacitance boosting operating voltage, wherein the capacitance boostingoperating voltage is determined by the following equation:

$V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}}$

where G₁ is conductance of the ferroelectric film, C₁ is capacitance ofthe ferroelectric film, G₂ is conductance of the dielectric film, C₂ iscapacitance of the dielectric film, ω is the angular frequency of thecontrol voltage, Ps is polarization of the ferroelectric film when theelectric field E_(FM) is applied to the ferroelectric film, α is astability parameter, and β is a skewness parameter.

A magnitude ratio (|Z₂|/|Z₁|) of the impedance of the dielectric film tothe impedance of the ferroelectric film may be 0.01 or greater.

When the control voltage is equal to the capacitance boosting operatingvoltage, the current density of current flowing through the dielectricfilm and the ferroelectric film may be 1 mA/cm² or less.

Spontaneous polarization of the ferroelectric film may be 20 μC/cm² orgreater.

A dielectric dissipation factor of the dielectric film may be 0.1 orless.

In an aspect, provided is an electronic device. The electronic devicemay include a first electrode; a second electrode on the firstelectrode; a ferroelectric film between the first electrode and thesecond electrode, the ferroelectric film having a first impedance; and adielectric film between the ferroelectric film and the second electrode,the dielectric film having a second impedance, wherein the ferroelectricfilm and the dielectric film are configured to have a capacitanceboosting operating voltage substantially equal to a control voltageapplied between the first electrode and the second electrode, andwherein the capacitance boosting operating voltage is determined byEquation 1:

$\begin{matrix}{V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}} & \left\lbrack {{Equation}1} \right\rbrack\end{matrix}$

where V_(MAX) is the capacitance boosting operating voltage, Z₁ is thefirst impedance, Z₂ is the second impedance, t_(F) is a thickness of theferroelectric film, and E_(FM) is an electric field applied to theferroelectric film having a maximum polarization change.

In an aspect, provided is a capacitor. The capacitor may include a firstelectrode; a second electrode on the first electrode; and an insulatingstructure, the insulating structure including a ferroelectric filmbetween the first electrode and the second electrode, the ferroelectricfilm having a first impedance and a dielectric film between theferroelectric film and the second electrode, the dielectric film havinga second impedance, wherein the ferroelectric film and the dielectricfilm are configured to have a capacitance boosting operating voltagesubstantially equal to a control voltage applied between the firstelectrode and the second electrode, and wherein the capacitance boostingoperating voltage is determined by Equation 1:

$\begin{matrix}{V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}} & \left\lbrack {{Equation}1} \right\rbrack\end{matrix}$

where V_(MAX) is the capacitance boosting operating voltage, Z₁ is thefirst impedance, Z₂ is the second impedance, t_(F) is a thickness of theferroelectric film, and E_(FM) is an electric field applied to theferroelectric film having a maximum polarization change.

The ferroelectric film may include a conductance component and acapacitance component connected in parallel, and the dielectric film mayinclude a conduct. An angular frequency of the control voltage may bedetermined such that the control voltage is equal to the capacitanceboosting operating voltage, and the capacitance boosting operatingvoltage is determined by Equation 2:

$\begin{matrix}{V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}}} & \left\lbrack {{Equation}2} \right\rbrack\end{matrix}$

where G₁ is conductance of the ferroelectric film, C₁ is capacitance ofthe ferroelectric film, G₂ is conductance of the dielectric film, C₂ iscapacitance of the dielectric film, ω is the angular frequency of thecontrol voltage, Ps is polarization of the ferroelectric film when theelectric field E_(FM) is applied to the ferroelectric film, α is astability parameter, and β is a skewness parameter.

A magnitude ratio (|Z₂|/|Z₁|) of the impedance of the dielectric film tothe impedance of the ferroelectric film may be 0.01 or greater.

The current density of current flowing through the dielectric film andthe ferroelectric film may be 1 mA/cm² or less.

Spontaneous polarization of the ferroelectric film may be 20 μC/cm² orgreater.

A dielectric dissipation factor of the dielectric film may be 0.1 orless.

In an aspect, provided is a transistor including a substrate, thesubstrate including a source region and a drain region spaced apart by achannel region; and a gate structure on the channel region, the gatestructure including a dielectric film, a ferroelectric film, and a gateelectrode sequentially provided on the channel region, wherein theferroelectric film, having a first impedance, and the dielectric film,having a second impedance, are configured to have a capacitance boostingoperating voltage substantially equal to a control voltage appliedbetween the gate electrode and the channel layer, and the capacitanceboosting operating voltage is determined by Equation 1:

$\begin{matrix}{V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}} & \left\lbrack {{Equation}1} \right\rbrack\end{matrix}$

where V_(MAX) is a capacitance boosting operating voltage, Z₁ is thefirst impedance, Z₂ is the second impedance, t_(F) is a thickness of theferroelectric film, and E_(FM) is an electric field applied to theferroelectric film having the maximum polarization change producedthereto.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certainembodiments of the disclosure will be more apparent from the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a cross-sectional view of a capacitor according to an exampleembodiment;

FIG. 2 is a circuit view of the capacitor shown in FIG. 1 ;

FIG. 3 is a cross-sectional view of a transistor according to an exampleembodiment;

FIG. 4 illustrates a circuit configuration of a memory cell of a memorydevice including a semiconductor device and a capacitor;

FIG. 5 illustrates a structure of a trench capacitor-type dynamic randomaccess memory (DRAM); and

FIG. 6 shows a schematic of a circuit that may include theaforementioned electronic devices according to some example embodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of whichare illustrated in the accompanying drawings, wherein like referencenumerals refer to like elements throughout. In this regard, the presentembodiments may have different forms and should not be construed asbeing limited to the descriptions set forth herein. Accordingly, theembodiments are merely described below, by referring to the figures, toexplain aspects. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items. Expressionssuch as “at least one of,” when preceding a list of elements, modify theentire list of elements and do not modify the individual elements of thelist.

Hereinafter, embodiments of the present disclosure will be described infurther detail with reference to the accompanying drawings. In thedrawings, the same reference numerals refer to the elements, and thesizes of various components are exaggerated or reduced for clarity andbrevity. Meanwhile, the following embodiment are presented by way ofexample only, and various changes and modifications may be made from thedescription of these embodiments.

In the following description, when an element is referred to as being“above” or “on” another element, it can be directly on the other elementin a contact manner or in a non-contact manner.

When the terms “about” or “substantially” are used in this specificationin connection with a numerical value, it is intended that the associatednumerical value includes a manufacturing tolerance (e.g., ±10%) aroundthe stated numerical value. Moreover, when the words “generally” and“substantially” are used in connection with geometric shapes, it isintended that precision of the geometric shape is not required but thatlatitude for the shape is within the scope of the disclosure. Further,regardless of whether numerical values or shapes are modified as “about”or “substantially,” it will be understood that these values and shapesshould be construed as including a manufacturing or operationaltolerance (e.g., ±10%) around the stated numerical values or shapes.

An expression used in the singular encompasses the expression of theplural, unless it has a clearly different meaning in the context. Inaddition, it will be understood that the term “comprising or including”specifies the addition and/or presence of one or more other components,but does not preclude the possibility of excluding the stated componentsfeatures, unless the context clearly indicates otherwise.

FIG. 1 is a cross-sectional view of a capacitor according to an exampleembodiment. FIG. 2 is a circuit view of the capacitor shown in FIG. 1 .Referring to FIGS. 1 and 2 , a capacitor 10, including a first electrode310, an insulating structure IS and a second electrode 320. Theinsulating structure may include a ferroelectric film 100 and adielectric film 200. The ferroelectric film 100 may include aferroelectric material. A ferroelectric material refers to anon-conductor or a dielectric material exhibiting spontaneouspolarization, and is distinguished from a multiferroic material thatpossesses two or more ferroic properties including, for example,ferroelectricity, ferroelasticity, ferromagnetism, and/oranti-ferromagnetism. Examples of the ferroelectric material may includeat least one of an oxide ferroelectric material, a polymer ferroelectricmaterial, a fluoride ferroelectric material (such as BaMgF₄ (BMF)),and/or a ferroelectric semiconductor.

Examples of the oxide ferroelectric material include perovskiteferroelectric materials such as PbZr_(x)Ti_(1-x)O₃ (PZT), BaTiO₃,PbTiO₃, pseudo-ilmenite ferroelectric materials such as LiNbO₃ orLiTaO₃, tungsten-bronze (TB) ferroelectric materials such as PbNb₃O₆ andBa₂NaNb₅O₁₅, bismuth layer-structured ferroelectric materials such asSrBi₂Ta₂O₉ (SBT), (Bi,La)₄Ti₃O₁₂ (BLT), or Bi₄Ti₃O₁₂, pyrochloreferroelectric materials such as La₂Ti₂O₇, solid solutions thereof, andrare-earth ferroelectric materials such as RMnO₃ and Pb₅Ge₃O₁₁ (PGO)including a rare-earth element such as Y, Er, Ho, Tm, Yb, and/or Lu.Examples of the polymer ferroelectric material may include at least oneof polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDFterpolymer, cyano-polymer, and/or copolymers thereof. Examples of theferroelectric semiconductor may include 2-6 group compounds includingCdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, and CdFeSe.

The ferroelectric material may have spontaneous polarization. Forexample, the spontaneous polarization of the ferroelectric film 100 maybe 20 μC/cm² or greater. The ferroelectric film 100 may include aconductance component and a capacitance component connected in parallel.Impedance of the ferroelectric film 100 will later be described.

The dielectric film 200 may include a material capable of achieving adesired capacitance. For example, as the integration level of anintegrated circuit device including the capacitor 10 is increased, anarea occupied by the capacitor 10 is gradually reduced, and thusdielectrics having a high dielectric constant may be favorably used. Thedielectric film 200 may include a material having a high dielectricconstant. The high dielectric constant may mean a dielectric constanthigher than that of silicon oxide. In an embodiment, the dielectric filmmay include a dielectric metal oxide. The dielectric metal oxide mayinclude, for example, at least one of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr,Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu. For example, the dielectric film200 may include HfO₂, ZrO₂, CeO₂, La₂O₃, Ta₂O₃, or TiO₂. The dielectricfilm 200 may have a single layered structure or multiple layeredstructures. The dielectric film, for example, may include aheterostructure including one or more dielectric metal oxides, and/or ahomostructure including one dielectric metal oxide. The thickness of thedielectric film 200 may be determined based on the desired capacitancefor the capacitor. For example, the dielectric film 200 may have athickness of 10 nanometers (nm) or less.

The dielectric film 200 may include a conductance component and acapacitance component connected in parallel. Impedance of the dielectricfilm 200 will later be described. In an embodiment, a dielectricdissipation factor of the dielectric film may be 1 or less.

The first electrode 310 may be at a side opposite to the dielectric film200 with respect to the ferroelectric film 100. For example, the firstelectrode 310 may directly contact the ferroelectric film 100 and notthe dielectric film 200. The first electrode 310 may include anelectrically conductive material. For example, the first electrode 310may include a metal, a metal nitride, a metal oxide, a carbon-basedconductor, or a combination thereof. For example, the first electrode310 may include at least one of Au, Al, TiN, MoN, CoN, TaN, TiAlN,TaAlN, W, Ru, RuO₂, SrRuO₃, Jr, IrO₂, Pt, PtO, SrRuO₃ (SRO),((Ba,Sr)RuO₃) (BSRO), CaRuO₃ (CRO), (La,Sr)CoO₃ (LSCO), graphene, and/ora combination thereof.

The second electrode 320 may be provided at a side opposite to theferroelectric film 100 with respect to the dielectric film 200. Forexample, the second electrode 320 may directly contact the dielectricfilm 200 and not the ferroelectric film 100. The second electrode 320may include an electrically conductive material. For example, the secondelectrode 320 may include a metal, a metal nitride, a metal oxide, aconductive carbon, or a combination thereof. For example, the secondelectrode 320 may include at least one of Au, Al, TiN, MoN, CoN, TaN,TiAlN, TaAlN, W, Ru, RuO₂, SrRuO₃, Jr, IrO₂, Pt, PtO, SrRuO₃ (SRO),((Ba,Sr)RuO₃) (BSRO), CaRuO₃ (CRO), (La,Sr)CoO₃ (LSCO), graphene, and/ora combination thereof. In an example embodiment, the first electrode310, the ferroelectric film 100, the dielectric film 200, and the secondelectrode 320 may be sequentially stacked on a substrate (not shown),thereby forming a capacitor 10.

Referring to FIG. 2 , the ferroelectric film 100 may be represented by aconductance component and a capacitance component electrically connectedin parallel. In the following description, the conductance component ofthe ferroelectric film 100 may be referred to as first conductance G1,and the capacitance component of the ferroelectric film 100 may bereferred to as first capacitance C1. For example, the ferroelectric film100 may have a first impedance. The dielectric film 200 may also includea conductance component and a capacitance component electricallyconnected in parallel. In the following description, the conductancecomponent of the dielectric film 200 may be referred to as secondconductance G2. The capacitance component of the dielectric film 200 maybe referred to as second capacitance C2. That is, the dielectric film200 may have a second impedance.

A control voltage may be applied to the capacitor 10 through the firstelectrode 310 and/or the second electrode 320. For example, the controlvoltage may be an alternating-current voltage having an angularfrequency ω. The control voltage may be substantially the same as thecapacitance boosting operating voltage that generates a capacitanceboosting effect in the ferroelectric film 100. The capacitance boostingeffect refers to a sharp increase in the capacitance of theferroelectric film 100. The capacitance boosting effect may be generatedwhen the ferroelectric film 100 has negative capacitance.

The capacitance boosting operating voltage may be expressed by thefollowing Equation (1):

$\begin{matrix}{V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}{E_{FM}.}}} & \left\lbrack {{Equation}1} \right\rbrack\end{matrix}$

where V_(MAX) is a capacitance boosting operating voltage, Z₁ isimpedance of the ferroelectric film, Z₂ is impedance of the dielectricfilm, t_(F) is a thickness of the ferroelectric film, and E_(FM) is anelectric field applied to the ferroelectric film having a maximumpolarization change.

In Equation (1), the thickness T_(F) of the ferroelectric film 100 andthe electric field E_(FM) applied to the ferroelectric film 100 havingthe maximum polarization change produced thereto have fixed values, andthus the capacitance boosting operating voltage V_(MAX) may becontrolled by adjusting the amplitude ratio of the impedance Z₁ of theferroelectric film 100 to the impedance Z₂ of the dielectric film. Forexample, a magnitude ratio (|Z₂|/|Z₁|) of the impedance Z₂ of thedielectric film 200 to the impedance Z₁ of the ferroelectric film 100may be 0.01 or greater.

The electrical field applied to the ferroelectric film having themaximum polarization change produced thereto may be an electric field inwhich the value of dP/dE₁ is largest. Here, P is polarization of theferroelectric film, and E_(F) is an electric field applied to theferroelectric film. The impedance Z₁ of the ferroelectric film 100 maybe expressed by Equation 3:

$\begin{matrix}{Z_{1} = {\frac{G_{1}}{G_{1}^{2} + {\omega^{2}C_{1}^{2}}} - {j\omega\frac{C_{1}}{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}}}} & \left\lbrack {{Equation}3} \right\rbrack\end{matrix}$

where G₁ is conductance of the ferroelectric film, C₁ is capacitance ofthe ferroelectric film, and ω is the angular frequency of the controlvoltage.

The impedance Z₂ of the dielectric film 200 may be expressed by thefollowing equation 3:

$\begin{matrix}{Z_{2} = {\frac{G_{2}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}} - {j\omega\frac{C_{2}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}}} & \left\lbrack {{Equation}3} \right\rbrack\end{matrix}$

where G₂ is conductance of the dielectric film, C₂ is capacitance of thedielectric film, and ω is the angular frequency of the control voltage.

The electric field E_(F) applied to the ferroelectric film 100 may beexpressed by the following equation 4:

E _(F)=2αP _(S)+4βP _(S) ³  [Equation 4]

where Ps is polarization of the ferroelectric film when the electricfield E_(FM) is applied to the ferroelectric film, α is a stabilityparameter, and β is a skewness parameter.

The stability parameter α and the skewness parameter β may be acquiredby performing a Landau fitting process on a polarization-electric fieldcurve of the ferroelectric film 100.

When Equations 2 to 4 are substituted for Equation (1), the capacitanceboosting operating voltage V_(MAX) may be expressed by the followingEquation 5:

$\begin{matrix}{V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){{t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}.}}} & \left\lbrack {{Equation}5} \right\rbrack\end{matrix}$

In Equation 5, the first conductance G₁, the first capacitance C₁, thesecond conductance G₂, the second capacitance C₂, the thickness t_(F) ofthe ferroelectric film 100, the stability parameter (α), the skewnessparameter (β), and the polarization Ps of the ferroelectric film whenthe electric field E_(FM) is applied to the ferroelectric film, may havefixed values. Therefore, the capacitance boosting operating voltageV_(MAX) may be controlled by adjusting the angular frequency ω of thecontrol voltage.

In an example embodiment, the current density of current flowing throughthe ferroelectric film 100 and the dielectric film 200 may be 1 mA/cm²or less.

The control voltage applied between the first electrode 310 and thesecond electrode 320 may be determined according to a semiconductordevice (e.g., DRAM) employing the capacitor 10. The present disclosuremay provide the capacitor 10 in which a magnitude ratio (|Z₂|/|Z₁|) ofthe impedance of the dielectric film 200 to the impedance of theferroelectric film 100 is determined such that the control voltage isequal to capacitance boosting operating voltage. The present disclosuremay provide the capacitor 10 in which the angular frequency co of thecontrol voltage is determined such that the control voltage is equal tothe capacitance boosting operating voltage.

FIG. 3 is a cross-sectional view of a transistor according to an exampleembodiment. For brevity, descriptions of substantially the same contentas described above with reference to FIGS. 1 and 2 may not be given.

Referring to 3, a transistor 20 may include a substrate 400, a sourceregion SD1, a drain region SD2, a channel region CR between the sourceregion SD1 and drain region SD2, an insulating structure IS, and a gateelectrode 330. The insulating structure IS may include a ferroelectricfilm 100 and a dielectric film 200.

The substrate 400 may include a semiconductor material. For example, thesubstrate 400 may be a silicon (Si) substrate, a germanium (Ge)substrate 400, and/or a silicon germanium (SiGe) substrate. Thesubstrate 400 may be of a first conductivity type. For example, thefirst conductivity type may be an n type. In the case wherein thesubstrate 400 includes a semiconductor material, the substrate 400 mayinclude the channel region CR. In this case, the channel region CR maybe a doped section of substrate 400. The channel region may act like anelectrode in a metal-oxide semiconductor capacitor (MOS capacitor). Forexample, in the case wherein the substrate has an n-type conductivity,the transistor may include a p-type MOS (pMOS) capacitor with holes asthe carriers in the inversion type. In this case, the MOS structure mayperform as a MOS capacitor when the transistor is in an “ON” state, forexample, when a voltage is applied to the gate electrode 330.

The source region SD1 and the drain region SD2 may be on the substrate400. The source region SD1 and the drain region SD2 may be spaced apartfrom each other in a direction parallel to a top surface of thesubstrate 400. The source region SD1 and the drain region SD2 may beformed by injecting impurities into a top portion of the substrate 400.For example, the source region SD1 and the drain region SD2 may be of asecond conductivity type different from the first conductivity type. Forexample, the second conductivity type may be a p type. The source regionSD1 and the drain region SD2 may also include electrodes on top of thesource region SD1 and the drain region SD2. The electrodes may includean electrically conductive material.

The ferroelectric film 100, the dielectric film 200, and the gateelectrode 330 may be between the source region SD1 and the drain regionSD2. The ferroelectric film 100, the dielectric film 200, and the gateelectrode 330 may be sequentially stacked on the substrate 400. Forexample, the ferroelectric film 100, the dielectric film 200, and thegate electrode 330 may be sequentially stacked over the channel regionCR. The ferroelectric film 100 and the dielectric film 200 may besubstantially the same as those described with reference to FIG. 1 .

The gate electrode 330 may include an electrically conductive material.For example, the gate electrode 330 may include aluminum (Al), gold(Au), tungsten (W), or a combination thereof. A control voltage may beapplied between the gate electrode 330 and the substrate 400. Forexample, the control voltage may be applied to the gate electrode 330,and the substrate 400 may be grounded. For example, the control voltagemay be an alternating-current voltage having an angular frequency ω. Thestructure including the ferroelectric film 100 and the dielectric film200 stacked may have a capacitance boosting effect that the capacitanceis greatly increased at the capacitance boosting operating voltage(e.g., V_(MAX) in Equations 1 and 5). For example, the capacitanceboosting effect may be generated by the ferroelectric film 100 havingnegative capacitance.

The control voltage applied between the gate electrode 330 and thesubstrate 400 may be determined in advance. The present disclosure mayprovide the transistor 20 in which a magnitude ratio (|Z₂|/|Z₁|) of theimpedance of the dielectric film 200 to the impedance of theferroelectric film 100 is determined such that the control voltage isequal to the capacitance boosting operating voltage. The presentdisclosure may provide the transistor 20 in which the angular frequencyω of the control voltage is determined such that the control voltage isequal to the capacitance boosting operating voltage.

The transistor 20 and the capacitor 10 described above together mayconstitute a memory cell. For example, FIG. 4 illustrates a circuitconfiguration of a memory cell 30 of a memory device including thetransistor 20 and the capacitor 10. FIG. 5 illustrates an exampleembodiment of an integrated circuit design including the memory cell.Referring to FIG. 4 , the memory cell 30 may include the transistor 20and the capacitor 10 electrically connected to the source region SD1 ofthe transistor 20. The memory device may include a plurality of bitlines and a plurality of word lines, and may further include a pluralityof the memory cells illustrated in FIG. 4 . Each word line may beelectrically connected to the gate electrode 330 of the transistor 20,and each bit line may be electrically connected to the drain region SD2of the transistor 20. The first electrode 310 of the capacitor 10 may beelectrically connected to the source region SD1 of the transistor 20,and the second electrode 320 of the capacitor 10 may be connected to avoltage controller configured to control the angular frequency of acontrol voltage applied to the capacitor 10.

FIG. 5 illustrates a structure of a trench capacitor-type dynamic randomaccess memory (DRAM).

Referring to FIG. 5 , on a semiconductor substrate 520, a deviceisolation region may be defined with a field oxide film 521, and a gateelectrode 523 and source/drain impurity regions 522 and 522′ may beformed in the device isolation region. A gate oxide layer 529 may beformed between the gate electrode 523 and the semiconductor substrate520. An oxide film may be formed as an interlayer insulating film 524. Aregion not to be a trench may be capped with a trench buffer layer, anda part of the source region 522 may be open to form a contact portion.

A trench is formed in a sidewall of the interlayer insulating film 524,and a sidewall oxide film 525 may be formed over the entire sidewall ofthe trench. The sidewall oxide film 525 may compensate for damage in thesemiconductor substrate caused by etching to form the trench, and mayserve as a dielectric film between the semiconductor substrate 520 and astorage electrode 526. A sidewall portion of part of the source region522, except for the other part of the source region near the gateelectrode 523, may be entirely exposed.

A PN junction (not illustrated) may be formed in the sidewall portion ofthe source region by impurity implantation. The trench may be formed inthe source region 522. A sidewall of the trench near the gate maydirectly contact the source region 522, and the PN junction may beformed by additional impurity implantation into the source region.

A storage electrode 526 may be formed on part of the interlayerinsulating film 524, the exposed source region 522, and the surface ofthe sidewall oxide film 525 in the trench. The storage electrode 526 maybe formed to contact the entire source region 522 in contact with theupper sidewall of the trench, in addition to the part of the sourceregion 522 near the gate electrode 523. Next, an insulating film 527 asa capacity dielectric film may be formed along the upper surface of thestorage electrode 526, and a polysilicon layer as a plate electrode 528may be formed thereon, thereby completing a trench capacitor type DRAM.The insulating film 527, and/or the interlayer insulating film 524, forexample, may be an embodiment of the insulating structure IS including aferroelectric film 100 and a dielectric film 200.

The aforementioned electronic devices including an insulating structureIS including a ferroelectric film 100 and a dielectric film 200 may beapplied to various electronic circuit devices including a transistor,for example as part of processing circuitry and/or memory.

FIG. 6 shows a schematic of a circuit that may include theaforementioned electronic devices according to some example embodiments.

As shown, the electronic device 600 includes one or more electronicdevice components, including a processor (e.g., processing circuitry)610 and a memory 620 that are communicatively coupled together via a bus630.

The processing circuitry 610, may be included in, may include, and/ormay be implemented by one or more instances of processing circuitry suchas hardware including logic circuits, a hardware/software combinationsuch as a processor executing software; or a combination thereof. Forexample, the processing circuitry 600 may include, but is not limitedto, a central processing unit (CPU), an application processor (AP), anarithmetic logic unit (ALU), a graphic processing unit (GPU), a digitalsignal processor, a microcomputer, a field programmable gate array(FPGA), a System-on-Chip (SoC) a programmable logic unit, amicroprocessor, or an application-specific integrated circuit (ASIC),etc. In some example embodiments, the memory 620 may include anon-transitory computer readable storage device, for example a solidstate drive (SSD), storing a program of instructions, and the processingcircuitry 600 may be configured to execute the program of instructionsto implement the functionality of the electronic device 600.

In some example embodiments, the electronic device 600 may include oneor more additional components 640, coupled to bus 630, which mayinclude, for example, a power supply, a light sensor, a light-emittingdevice, any combination thereof, or the like. In some exampleembodiments, one or more of the processing circuitry 610, memory 620,and/or one or more additional components 640 may include an electronicdevice including electrodes and an insulating structure including aferroelectric film 100 and a dielectric film 200, as described above,such that the one or more of the processing circuitry 610, memory 620,and/or one or more additional components 640, and thus, the electronicdevice 600, may include the transistor 20 (refer to FIG. 3 ), thecapacitor 10 (refer to FIG. 3 ), and/or the memory cell 30 (refer toFIG. 5 ).

It should be understood that embodiments described herein should beconsidered in a descriptive sense only and not for purposes oflimitation. Descriptions of features or aspects within each embodimentshould typically be considered as available for other similar featuresor aspects in other embodiments. While one or more embodiments have beendescribed with reference to the figures, it will be understood by thoseof ordinary skill in the art that various changes in form and detailsmay be made therein without departing from the spirit and scope asdefined by the following claims.

What is claimed is:
 1. An electronic device comprising: a firstelectrode on a substrate; a second electrode spaced apart from the firstelectrode such that the first electrode is between the second electrodeand the substrate; and an insulating structure between the firstelectrode and the second electrode, the insulating structure including aferroelectric film and a dielectric film, the ferroelectric film havinga first impedance and the dielectric film having a second impedance,wherein the ferroelectric film and the dielectric film are configured tohave a capacitance boosting operating voltage substantially equal to acontrol voltage applied between the first electrode and the secondelectrode, and wherein the capacitance boosting operating voltage isdetermined by the following equation:$V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}$where V_(MAX) is the capacitance boosting operating voltage, Z₁ is thefirst impedance, Z₂ is the second impedance, t_(F) is a thickness of theferroelectric film, and E_(FM) is an electric field applied to theferroelectric film having a maximum polarization change.
 2. Theelectronic device of claim 1, wherein the first impedance (Z₁) isdetermined based on a conductance component (G₁) of the ferroelectricfilm and a capacitance component (C₁) of the ferroelectric film, and thesecond impedance (Z₂) is determined based on a conductance component(G₂) of the dielectric film and a capacitance component (C₂) of thedielectric film.
 3. The electronic device of claim 1, wherein an angularfrequency of the control voltage is determined such that the controlvoltage is equal to the capacitance boosting operating voltage, and thecapacitance boosting operating voltage is determined by the followingequation:$V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}}$where$\sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}$ represents the |Z₂|/|Z₁|, (2αP_(s)+4βP_(S) ³) represents the E_(FM), G₁is conductance of the ferroelectric film, C₁ is capacitance of theferroelectric film, G₂ is conductance of the dielectric film, C₂ iscapacitance of the dielectric film, ω is the angular frequency of thecontrol voltage, Ps is polarization of the ferroelectric film when theelectric field is applied to the ferroelectric film, α is a stabilityparameter, and β is a skewness parameter.
 4. The electronic device ofclaim 1, wherein the magnitude ratio (|Z₂|/|Z₁|) of the impedance of thedielectric film to the first impedance of the ferroelectric film is 0.01or greater.
 5. The electronic device of claim 1, wherein current densityof current flowing through the dielectric film and the ferroelectricfilm is 1 mA/cm² or less.
 6. The electronic device of claim 1, whereinspontaneous polarization of the ferroelectric film is 20 μC/cm² or more.7. The electronic device of claim 1, wherein a dielectric dissipationfactor of the dielectric film is 0.1 or less.
 8. The electronic deviceof claim 1, wherein the ferroelectric film includes at least one of anoxide ferroelectric material, a polymer ferroelectric material, afluoride ferroelectric material, and a ferroelectric semiconductor. 9.The electronic device of claim 8, wherein the oxide ferroelectricmaterial includes at least one of a perovskite ferroelectric material, atungsten-bronze ferroelectric material, a bismuth layer-structuredferroelectric material, and a rare-earth ferroelectric material.
 10. Theelectronic device of claim 1, wherein the dielectric film has a highdielectric constant.
 11. The electronic device of claim 1, wherein thedielectric film is an oxide, and the oxide includes at least one of Ca,Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.12. The electronic device of claim 1, wherein the dielectric film has athickness of 10 nanometers or less.
 13. The electronic device of claim1, wherein the first electrode includes a conductive material, thesecond electrode includes a conductive material, and the electronicdevice is a capacitor.
 14. The electronic device of claim 1, wherein thefirst electrode includes a semiconductor, the second electrode includesa conductive material, and the electronic device is a transistor. 15.The electronic device of claim 14, wherein the electronic device isconfigured to perform as a metal-oxide-semiconductor capacitor during anON operation of the transistor.
 16. The electronic device of claim 14,further comprising: a source region, a drain region, and a channelregion in the substrate, wherein the second electrode is a gateelectrode.
 17. The electronic device of claim 16, wherein the channelregion has an opposite conductivity type to the source region and thedrain region.
 18. The electronic device of claim 17, wherein the channelregion as an n-type conductivity, and the source region and the drainregion have a p-type conductivity.
 19. A method of controlling acapacitor comprising a first electrode on a substrate, a secondelectrode spaced apart from the first electrode such that the firstelectrode is between the second electrode and the substrate, and aninsulating structure including a ferroelectric film and a dielectricfilm between the first electrode and the second electrode, theferroelectric film having a first impedance and the dielectric filmhaving a second impedance, the method comprising: controlling animpedance of the ferroelectric film and an impedance of the dielectricfilm such that a control voltage applied between the first electrode andthe second electrode is substantially equal to a capacitance boostingoperating voltage, wherein the capacitance boosting operating voltage isdetermined by the following equation:$V_{MAX} = {\left( {1 + \frac{❘Z_{2}❘}{❘Z_{1}❘}} \right)t_{F}E_{FM}}$where V_(MAX) is a capacitance boosting operating voltage, Z₁ is theimpedance of the ferroelectric film, Z₂ is the impedance of thedielectric film, t_(F) is a thickness of the ferroelectric film, andE_(FM) is an electric field applied to the ferroelectric film having amaximum polarization change.
 20. The method of claim 19, wherein thefirst impedance (Z₁) is determined based on a conductance component (G₁)of the ferroelectric film and a capacitance component (C₁) of theferroelectric film, and the second impedance (Z₂) is determined based ona conductance component (G₂) of the dielectric film and a capacitancecomponent (C₂) of the dielectric film.
 21. The method of claim 19,further comprising: controlling an angular frequency of the controlvoltage such that the control voltage is equal to the capacitanceboosting operating voltage, wherein the capacitance boosting operatingvoltage is determined by the following equation:$V_{MAX} = {\left( {1 + \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}}} \right){t_{F}\left( {{2\alpha P_{S}} + {4\beta P_{S}^{3}}} \right)}}$where$\left( \sqrt{\frac{G_{1}^{2} + {\omega^{2}C_{1}^{2}}}{G_{2}^{2} + {\omega^{2}C_{2}^{2}}}} \right)$ represents the |Z₂|/|Z₁|, (2αP_(s)+4βP_(S) ³) represents the E_(FM), G₁is conductance of the ferroelectric film, C₁ is capacitance of theferroelectric film, G₂ is conductance of the dielectric film, C₂ iscapacitance of the dielectric film, ω is the angular frequency of thecontrol voltage, Ps is polarization of the ferroelectric film when theelectric field E_(FM) is applied to the ferroelectric film, α is astability parameter, and β is a skewness parameter.
 22. The method ofclaim 19, wherein the magnitude ratio (|Z₂|/|Z₁|) of the first impedanceof the dielectric film to the impedance of the ferroelectric film is0.01 or greater.
 23. The method of claim 19, wherein when the controlvoltage is equal to the capacitance boosting operating voltage, acurrent density of current flowing through the dielectric film and theferroelectric film is 1 mA/cm² or less.
 24. The method of claim 19,wherein spontaneous polarization of the ferroelectric film is 20 pf/cm²or more.
 25. The method of claim 19, wherein a dielectric dissipationfactor of the dielectric film is 0.1 or less.